1. Field of the Invention
This invention relates generally to the field of compressed memory architecture in computer systems, and more specifically, to an improved method and apparatus for operating a main memory compressor.
2. Discussion of the Prior Art
Computer systems generally consist of one or more processors that execute program instructions stored within a mass storage medium. This mass storage medium is most often constructed of the lowest cost per bit, yet slowest storage technology, typically magnetic or optical media. To increase the system performance, a higher speed, yet smaller and more costly memory, known as the main memory, is first loaded with information from the mass storage for more efficient direct access by the processors. Even greater performance is achieved when a higher speed, yet smaller and more costly memory, known as a cache memory, is placed between the processor and main memory to provide temporary storage of recent/and or frequently referenced information. As the difference between processor speed and access time of the final storage increases, more levels of cache memory are provided, each level backing the previous level to form a storage hierarchy. Each level of the cache is managed to maintain the information most useful to the processor. Often more than one cache memory will be employed at the same hierarchy level, for example when an independent cache is employed for each processor. Caches have evolved into quite varied and sophisticated structures, but always address the tradeoff between speed and both cost and complexity, while functioning to make the most useful information available to the processor as efficiently as possible.
Recently, cost reduced computer system architectures have been developed that more than double the effective size of the main memory by employing high speed compression/decompression hardware based on common compression algorithms, in the path of information flow to and from the main memory. Processor access to main memory within these systems is performed indirectly through the compressor and decompressor apparatuses, both of which add significantly to the processor access latency costs. Large high speed cache memories are implemented between the processor and the compressor and decompressor hardware to reduce the frequency of processor references to the compressed memory, mitigating the effects the high compression/decompression latency. These caches are partitioned into cache lines, equal in size to the fixed information block size required by the compressor and decompressor.
Referring to FIG. 1, a block diagram of a prior art computer system 100 is shown. The computer system includes one or more processors 101 connected to a common shared memory controller 102 that provides access to a system main memory 103. The shared memory controller contains a compressor 104 for compressing fixed size information blocks into as small a unit as possible for ultimate storage into the main memory, a decompressor 105 for reversing the compression operation after the stored information is later retrieved from the main memory, and write queue 113 for queuing main memory store request information block(s) destined for the compressor. The processor data bus 108 is used for transporting uncompressed information between other processors and/or the shared memory controller. Information may be transferred to the processor data bus 108 from the main memory 103, either through or around the decompressor 105 via a multiplexor 111. Similarly, information may be transferred to the main memory 103 from the processor data bus 108 to the write queue 113 and then either through or around the compressor 104 via a multiplexor 112.
The main memory 103 is typically constructed of dynamic random access memory (DRAM) with access controlled by a memory controller 106. Addresses appearing on the processor address bus 107 are known as Real Addresses, and are understood and known to the programming environment. Addresses appearing on the main memory address bus 109 are known as Physical Addresses, and are used and relevant only between the memory controller and main memory DRAM. Memory Management Unit (MMU) hardware within the memory controller 106 is used to translate the real processor addresses to the virtual physical address space. This translation provides a means to allocate the physical memory in small increments for the purpose of efficiently storing and retrieving compressed and hence, variable size information.
The compressor 104 operates on a fixed size block of information, say 1024 bytes, by locating and replacing repeated byte strings within the block with a pointer to the first instance of a given string, and encoding the result according to a protocol. This process occurs through a byte-wise compare over a fixed length and is paced by a sequence counter, resulting in a constant completion time. The post process output block ranges from just a few bytes to the original block size, when the compressor could not sufficiently reduce the starting block size to warrant compressing at all. The decompressor 105 functions by reversing the compressor operation by decoding resultant compressor output block to reconstruct the original information block by inserting byte strings back into the block at the position indicated by the noted pointers. Even in the very best circumstances, the compressor is generally capable of only xc2xc-xc2xd the data rate bandwidth of the surrounding system. The compression and decompression processes are naturally linear and serial too, implying quite lengthy memory access latencies through the hardware.
FIG. 2 depicts a prior art main memory partitioning scheme 200. The main memory 205 is a logical entity because it includes the processor(s) information as well as all the required data structures necessary to access the information. The logical main memory 205 is physically partitioned from the physical memory address space 206. In many cases the main memory partition 205 is smaller than the available physical memory to provide a separate region to serve as a cache with either an integral directory, or one that is implemented externally 212. It should be noted that when implemented, the cache storage may be implemented as a region 201 of the physical memory 206, a managed quantity of uncompressed sectors, or as a separate storage array 114. In any case, when implemented, the cache controller requests accesses to the main memory in a similar manner as a processor would if the cache were not present.
The logical main memory 205 is partitioned into the sector translation table 202, with the remaining memory being allocated to sector storage 203 which may contain compressed or uncompressed information, free sector pointers, or any other information as long as it is organized into sectors. The sector translation table region size 211 varies in proportion to the real address space size which is defined by a programmable register within the system. Particularly, equation 1) governs the translation of the sector translation table region size as follows:                               sector_translation          ⁢          _table          ⁢          _size                =                                                            real_memory                ⁢                _size                                            compression_memory                ⁢                _size                                      ·            translation_table                    ⁢          _entry          ⁢          _size                                    1        )            
Each entry is directly mapped 210 to a fixed address range in the processor""s real address space, the request address being governed in accordance with equation 2) as follows:                               STT_entry          ⁢          _address                =                              (                                                            (                                      real_address                                          compression_block                      ⁢                      _size                                                        )                                ·                translation_table                            ⁢              _entry              ⁢              _size                        )                    +          offset_size                                    2        )            
For example, a mapping may employ a 16 byte translation table entry to relocate a 1024 byte real addressed compression block, allocated as a quantity 256 byte sectors, each located at the physical memory address indicated by a 25-bit pointer stored within the table entry. The entry also contains attribute bits 208 that indicate the number of sector pointers that are valid, size, and possibly other information. Every real address reference to the main memory causes the memory controller to reference the translation table entry 207 corresponding to the real address block containing the request address 210. For read requests, the MMU decodes the attribute bits 208, extracts the valid pointer(s) 209 and requests the memory controller to read the information located at the indicated sectors 204 from the main memory sectored region 203. Similarly, write requests result in the MMU and memory controller performing the same actions, except information is written to the main memory. However, if a write request requires more sectors than are already valid in the translation table entry, then additional sectors heed to be assigned to the table entry before the write may commence. Sectors are generally allocated from a list of unused sectors that is dynamically maintained as a stack or linked list of pointers stored in unused sectors. There are many possible variations on this translation scheme, but all involve a region of main memory mapped as a sector translation table and a region of memory mapped as sectors. Storage of these data structures in the DRAM based main memory provides the highest performance at the lowest cost, as well as ease of reverting the memory system into a typical direct mapped memory without compression and translation.
Since the compression and uncompression functions effectively encode and decode user data, any malfunction during the processes can produce seemingly correct, yet corrupted output. Further, implementing the compression/decompression hardware requires a prodigious quantity of (order 1 million) logic gates. Thus, the probability for a logic upset induced data corruption that goes undetected is significant. Special detection mechanisms within the compressor and decompressor can mitigate, but cannot provide significant fault coverage. Therefore, the need has arisen for an improved method of data management in a compressed memory system, without significant cost or complexity, to minimize the potential for a corrupted data to persist in the system without detection.
It is an object of the invention to provide a data management mechanism, within a compressed memory system, to maximize the integrity of the system operation through specific measures to guard against compression and decompression hardware induced data corruption going undetected within the system. This mechanism, sacrifices memory space (compressibility) to increase the overall reliability of the system.
It is a further object of the invention to provide a method and apparatus to compute a check code for a source data block, as the block is read in to the compressor, and append the final check code to the compressed result before storage into the compressed memory; and further, when the compressed result is read back from memory, the decompressor re-computes the check code as the decompressed data passes out of the decompressor to the requester, and compares the final computed check code with the check code appended to the received data to validate the integrity of the data block.
According to the invention, a standard 32-bit cyclic redundancy code (CRC) is computed over the uncompressed data block as it streams to the compressor. When the compression is complete and the data is to be stored in the compressed format (i.e., the data is compressible, such that a spatial advantage exists over storing the data in the uncompressed format), the CRC code is appended to the end of the compressed data block, and the associated block size is increased by the amount needed to store the code. Information that is stored in the uncompressed format, gains little benefit from the CRC as it is not encoded by the compressor, and hence is not covered by the CRC protection. Service of a memory read request, results in the decompression of a compressed block and recomputation of the standard 32-bit cyclic redundancy code (CRC) over the uncompressed data stream from the decompressor. Upon completion of the decompression of the block the appended 32-bit CRC is compared to the re-computed 32-bit CRC. When the two code are not equal, an uncorrectable error is signaled within the system to alert the operating system to the event. Uncompressed data blocks read from the memory bypass the decompressor and have no CRC associated with them.
Advantageously, such a method and system for detection of data corruption enables hardware compression to be used in enterprise class and other high reliability system applications.